Dual power supplies have been used in low power designs to reduce static and dynamic power. Higher supply voltage (VCCH) is typically used for circuits in critical paths, and lower supply voltage (VCCL) is used for circuits and non-critical paths. In one embodiment, the higher supply voltage is 1.1 volts, while the lower supply voltage may range between 0.8 and 1.1 volts. It should be appreciated that these voltages are exemplary for core regions of integrated circuits and are not meant to be limiting as the corresponding voltages may be any suitable voltage as long as the relative relationships between the voltages are maintained. With regard to programmable logic devices (PLD), switches are used to select between the higher supply voltage and lower supply voltage. Due to the configurable nature of the programmable logic device, a large number of switches are necessary to accommodate the flexibility provided by the PLD. It should he further appreciated that signals traveling from a VCCL region to a VCCH region need level converters between the two regions in order to avoid a large static current, which occurs when driving a gate in a VCCH region with a gate in a VCCL region.
Level converters have been implemented in various ways. However, common problems encountered include increased delays and relatively large switching currents. With hard wired logic the delays can be minimized as designers know where to place the level converters. When dealing with PLDs, level converters are required at each location where VCCL and VCCH can interface as a designer is unaware beforehand where level converters are needed for different user designs.
Thus, an improved level converter scheme and architecture are needed to minimize delays and contemporaneously reduce power consumption is needed.